"Customers leveraging these solutions to design with our Arria, Cyclone or Stratix FPGAs will achieve rapid design turn-around times with improved quality of results and higher levels of productivity."
"The team-design features within the Synplify synthesis tool complement the incremental compilation technology in our Quartus II software in order to help users dramatically reduce design iteration times," said Phil Simpson, senior manager, software technical marketing and EDA relationships at Altera Corporation. The Synplify FPGA synthesis tools' new team-design flow, improved runtime speeds and high quality of results will be critical for large-scale designs with up to two million logic cells." "We have been working closely with Synopsys to ensure that our mutual customers gain the power efficiency, performance-capacity and price-performance of our Virtex-6, Spartan-6 and new 28nm 7 series FPGAs. Synchronized support for DesignWare Library will greatly improve user productivity in FPGA-based design flows," said Tom Feist, senior director of marketing for ISE Design Suite at Xilinx.
"As the leading provider of FPGAs, we are excited to see Synopsys' commitment to making their high quality DesignWare IP available to FPGA designers. Designers implementing FPGAs for production applications or ASIC prototyping will benefit from the faster, easier-to-use Synplify-based design flows." "We enhanced the latest releases of Synplify Pro and Synplify Premier with these requirements in mind. "Designers increasingly require fast design turnaround, quick and accurate feedback on design performance and tools that improve the productivity of their geographically distributed design teams," said Ed Bard, senior director of marketing, Solutions Group at Synopsys. In addition, a unique team-design interface allows geographically distributed teams to work on portions of the design in parallel, accelerating logic synthesis performance and improving the quality of results (QoR) of their design. Comprehensive support for Synopsys DesignWare® Library datapath and building blocks components enables the use of common RTL from prototype to production. The new features in the 2010.09 release shorten logic synthesis runtimes and enable faster post-netlist incremental design turns.
(Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the availability of enhancements to its Synplify Pro® and Synplify® Premier FPGA synthesis tools.